/*
 * Copyright (c) 2003-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gou Pengfei
 *
 */

#ifndef __ARCH_TRIPS_ISA_TRAITS_HH__
#define __ARCH_TRIPS_ISA_TRAITS_HH__

//Trips is big-endian
namespace BigEndianGuest {}
#include <vector>

#include "arch/trips/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "arch/trips/constants.hh"
#include "arch/trips/opn_constants.hh"

class EDGEStaticInstPtr;
class StaticInstPtr;

namespace TripsISA {

using namespace BigEndianGuest;

/// Operand of TRIPS is 64-bit
typedef uint64_t OpSize;
/// Size of consumer ID
typedef uint16_t ConsumerID;

/// Block ID
typedef int64_t BlockID;
/// Chunk ID
typedef int ChunkID;
/// Inst ID
typedef int InstID;

/// Load/Store ID
typedef int LsID;
/// Exit ID
typedef uint32_t ExitID;

/// BType ID
typedef int8_t BTypeID;

typedef std::vector<uint32_t> HeaderInfo;

EDGEStaticInstPtr decodeInst(ExtMachInst, uint8_t);
StaticInstPtr decodeInst(ExtMachInst);

/// TRIPS instruction format related definitions
const uint32_t ChunkSize = 128;     // In bytes
const uint32_t ChunkSizeInWords = 32; // In words
const Addr ChunkOffset = ChunkSize - 1;
const Addr ChunkMask = ~(ChunkSize - 1);
const uint32_t MaxBlockSize = 5;    // In chunks
const uint8_t HeaderInfoSize = 4;  // In Words
const uint32_t StoreMaskNum = 32; // In bits
const uint32_t HeaderSize = 32; /// Header size in words
const uint32_t MaxInstsInBlock = 128; /// Max block size in insts
const uint32_t MaxLdstsInBlock = 32; /// Max load/stores in block
const uint32_t MaxExitsInBlock = 8; /// Max exits in block
const uint8_t NumBranchType = 4; /// Number of branch types

// Trips Does NOT have a delay slot
#define ISA_HAS_DELAY_SLOT 0

const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;

////////////////////////////////////////////////////////////////////////
//
//  Translation stuff
//

const Addr PteShift = 3;
const Addr NPtePageShift = PageShift - PteShift;
const Addr NPtePage = ULL(1) << NPtePageShift;
const Addr PteMask = NPtePage - 1;

// User Virtual
const Addr USegBase = ULL(0x0);
const Addr USegEnd = ULL(0x000003ffffffffff);

// Kernel Direct Mapped
const Addr K0SegBase = ULL(0xfffffc0000000000);
const Addr K0SegEnd = ULL(0xfffffdffffffffff);

// Kernel Virtual
const Addr K1SegBase = ULL(0xfffffe0000000000);
const Addr K1SegEnd = ULL(0xffffffffffffffff);

// For loading... XXX This maybe could be USegEnd?? --ali
const Addr LoadAddrMask = ULL(0xffffffffff);

////////////////////////////////////////////////////////////////////////
//
//  Interrupt levels
//
enum InterruptLevels
{
    INTLEVEL_SOFTWARE_MIN = 4,
    INTLEVEL_SOFTWARE_MAX = 19,

    INTLEVEL_EXTERNAL_MIN = 20,
    INTLEVEL_EXTERNAL_MAX = 34,

    INTLEVEL_IRQ0 = 20,
    INTLEVEL_IRQ1 = 21,
    INTINDEX_ETHERNET = 0,
    INTINDEX_SCSI = 1,
    INTLEVEL_IRQ2 = 22,
    INTLEVEL_IRQ3 = 23,

    INTLEVEL_SERIAL = 33,

    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
};

enum mode_type
{
    mode_kernel = 0,        // kernel
    mode_executive = 1,     // executive (unused by unix)
    mode_supervisor = 2,    // supervisor (unused by unix)
    mode_user = 3,          // user mode
    mode_number             // number of modes
};

// Constants Related to the number of registers

enum {
    LogVMPageSize = 12,       // 4K bytes
    VMPageSize = (1 << LogVMPageSize),

    BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned

    MachineBytes = 8,
    WordBytes = 4,
    HalfwordBytes = 2,
    ByteBytes = 1,
};

/** Flags for decoding insts. */
enum BlockStatus{
    Head = 0,
    Normal = 1,
    HeaderRead = 2,
    HeaderWrite = 3
};

/** Flags to indicate the status of a header code. */
enum HeaderStatus {
    HeaderNop = 0,
    ReadValid = 1,
    WriteValid = 2,
    ReadAndWriteValid = 3
};

enum WriteReadFlag{
    Write = 0,
    Read = 1
};

/// Dataflow token type generated by this intruction
enum DataflowTokenType {
    General = 0,
    Nullification,
    Exception,
    InvalidToken
};

enum PredStatus{
    PredTrue,
    PredFalse,
    NoPred
};

enum ConsumerType {
    WriteSlotOrNoTarget = 0,
    PredSlot,
    Operand0,
    Operand1,
    InvalidType
};

enum ConsumerSubType {
    NoTarget = 0,
    WriteSlot,
    InvalidSubType
};

enum Predication {
    Disable = 0,        
    PredUponFalse = 2,
    PredUponTrue = 3,
    Reserved
};

enum ExitType {
    seq = 0,
    branch,         
    call,
    ret,
    InvalidExitType
};

// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))
//const ExtMachInst NoopMachInst = 0x2ffe0000;

} // namespace AlphaISA

#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
